With the progress of the times and the development of the society, the function of semiconductor memory device is more and more important in the human society. At the same time, people have higher requirements on semiconductor memory performance, cost and so on. Due to the development of semiconductor technologies and processes, semiconductor memories with vertical channel transistors have been developed and successfully used in the industry. Such memory devices are often referred to as three-dimensional memory devices. Compared with the previous memory devices with only planar channel transistors, the three-dimensional memory device can obtain more storage nodes in the same chip area, thereby increasing the integration of the memory device and reducing the cost.
Considering the continuous scaling shrink of semiconductor process feature sizes, the process and structure for forming three-dimensional memory devices are faced with many challenges. One of the notable problems is that, referring to FIG. 13, in the illustrated three-dimensional memory structure, a lower select transistor 21 consists of an L-type SEG (Selective Epitaxial Growth) transistor including two segments of channel lengths L1 and L2. In the high-density integration process, it is necessary to reduce the width of the gate electrode and to further reduce the aperture. However, the high-temperature process in the fabrication of the memory device may make undesirable diffusion during the implantation of the common source region 22, as shown by the dotted line in FIG. 13, resulting in a pinch-off in the N+ region under the channel hole 23, making it difficult to batch erase the hole of the substrate 24.
Therefore, there is a need to provide a novel three-dimensional memory device and a method of manufacturing the same to overcome the above drawbacks of the prior art.